This application is based upon and claims priority of Japanese Patent Application No. 2000-030912, filed on Feb. 8, 2000, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to semiconductor memory devices, in particular, having a function of switching over power supplies to be used, for example, memories such as DRAMs (Dynamic Random Access Memories) including overdrive sense amplifiers.
2. Description of the Related Art
Recently, in a semiconductor memory device represented by a DRAM or the like which enlarges its capacity, a memory device increases its level of integration year after year, and the reduction of an element such as a transistor progresses year after year. Accordingly, a voltage which can be applied to a memory cell part is decreasing year after year from the viewpoints of less energy consumption and reliability.
However, a sense amplifier which amplifies a fine electric charge outputted from a memory cell of the DRAM decreases its driving capacity with the less voltage and hence the time for amplifying a bit line voltage is lengthened. This results in longer cycle time and access time of the DRAM. Therefore, an overdrive type sense amplifier is proposed in order to reduce the voltage which is applied to the memory cell part and to amplify the bit line voltage quickly by the sense amplifier.
FIG. 5A to FIG. 5E are illustrations showing partial structural examples and operations of the overdrive type sense amplifier in general. FIG. 5A is a circuit diagram showing one sense amplifier part taken from the sense amplifiers which are provided corresponding to memory cell arrays which are in a matrix state and comprise the DRAM.
As shown in FIG. 5A, the sense amplifier is connected to a bit line pair BL and /BL in a flip-flop structure. The drain of a transistor which comprises a not-shown memory cell is further connected to the bit line pair BL and /BL. The sense amplifier amplifies a differential voltage which occurs in the bit line pair BL and /BL according to an electric charge accumulated in a capacitance element of the memory cell which is accessed in reading-out of data.
At this time, the sense amplifier is activated by a signal lex which is supplied from a signal line connected commonly to high potential side terminals of the flip-flops and a signal lez which is supplied from a signal line connected commonly to low potential side terminals of the flip-flops. Namely, as shown in FIG. 5B and FIG. 5C, the signal lex changes to the low level while the signal lez changes to the high level, and the sense amplifier begins to be activated when these reach a certain level.
As shown in FIG. 5B, in driving the sense amplifier of the overdrive type sense amplifier, an external voltage (peripheral voltage) Vdd which has a higher level than an internal step-down voltage (core voltage) Viic as a voltage accumulated in the memory is supplied first as a power supply voltage Viid. Then, after a transitional overdrive time tovd, the power supply voltage Viid to be supplied is decreased to the internal step-down voltage Viic which is in the level of the voltage accumulated in the memory.
The change of its voltage levels of the bit line pair BL and /BL is shown in FIG. 5C. As shown in FIG. 5C, the voltage levels of the bit line pair BL and /BL become sharply disparate, and the bit line voltage is amplified in a short time. Thus, the bit line pair BL and /BL are driven in an early step of the drive by using the external voltage Vdd which has the higher level than the internal step-down voltage Viic, which makes it possible to shorten the time for amplifying the bit lines.
Incidentally, in an appropriate situation as shown in FIG. 5C, the voltage of the bit line pair BL and/BL is precharged to the voltage of the one-half level of the internal step-down voltage Viic after the amplification.
The overdrive time tovd is decided by a method of a fixed delay element according to a value obtained by a simulation or the like in designing the memory, and by a method of sensing its situation by separately providing a dummy sense amplifier for monitoring. (An application in relation to the latter method has been already filed with the Japanese Patent Office in the name of the present applicant.) In each of the methods, it is not the case that the overdrive time tovd is decided by sensing an electric charge of the actual bit line itself.
Moreover, there arises a need for a quick random access of the DRAM in recent years so that an FCRAM (Fast Cycle RAM) is developed as an example of the device for satisfying the need. The basic technology of this FCRAM is disclosed in WO 98/56004. The FCRAM, one memory block of which is further divided into sub-blocks, is a device which processes a narrower operation area of the sense amplifier by activating the sub-block which is selected by a row address only in the reading-out/writing-in of data, and precharges automatically when the processing completes.
FIG. 6 is a diagram showing a structural example when the overdrive type sense amplifier is applied to the FCRAM, which shows one memory block (bank).
In FIG. 6, a row decoder 1 decodes a row address signal and activates a word line to which the memory cell to be accessed is connected among the word lines (not shown) provided on each of the rows of the respective memory cell arrays (sub-blocks) 3 which are arranged in a matrix state.
A column decoder 2 decodes a column address signal, selects the bit line pair to which the memory cell to be accessed is connected among the bit line pair (not shown) provided on each of the columns of the respective memory cell arrays (sub-blocks) 3 which are arranged in a matrix state, and connects the selected bit line pair to a not-shown data-bus.
The sense amplifiers 4 amplify the differential voltage which occurs in the bit line pair according to the electric charge accumulated in the capacitance elements of the memory cells which are accessed in reading-out of data. The sense amplifiers 4 are arranged on each side of the memory cell arrays (sub-blocks) 3 which are arranged in a matrix state in one bank. Power supply wirings for the sense amplifiers (Viid) 5 are the wirings for supplying the power supply voltage to the respective sense amplifiers 4, which are connected in a mesh state to the memory cell arrays (sub-blocks) 3 and the sense amplifiers 4 which are arranged in a matrix state.
Power supply circuits PS1 to PS4 which supply overdrive power supplies are dispersed corresponding to the memory blocks, each of which includes pMOS (pchannel MOS) transistors 6-1 to 6-4, 7-1 to 7-4 for switching the power supplies. One pMOS transistors 6-1 to 6-4 are connected between the power supply wirings for the sense amplifiers (Viid) 5 and the power supplies of the external voltage Vdd, while the other pMOS transistors 7-1 to 7-4 are connected between the power supply wirings for the sense amplifiers (Viid) 5 and the power supplies of the internal step-down voltage Viic. These pMOS transistors 6-1 to 6-4, 7-1 to 7-4 comprise a drive circuit of the sense amplifier 4.
A Viid control circuit 8 controls the turning on/off of the pMOS transistors 6-1 to 6-4, 7-1 to 7-4 provided in each of the power supply circuits PS1 to PS4. When driving the sense amplifier 4 by turning on/off the pMOS transistors 6-1 to 6-4, 7-1 to 7-4, this Viid control circuit 8 supplies the external voltage Vdd which has the higher level than the internal step-down voltage Viic to the power supply wirings for the sense amplifiers (Viid) 5 by first turning on the pMOS transistors 6-1 to 6-4 on one hand concurrently.
Then, after a transitional overdrive time tovd, the pMOS transistors 6-1 to 6-4 on one hand are turned off and the pMOS transistors 7-1 to 7-4 on the other hand are turned on concurrently, whereby the internal step-down voltage Viic is supplied to the power supply wirings for the sense amplifiers (Viid) 5. Thus, overdrive of the sense amplifier 4 is operated and the quick amplification of the bit line voltage can be achieved.
FIG. 7 and FIG. 8 are diagrams comparing the numbers of sub-blocks (shown by hatching) which are activated by the reading-out/writing-in operations and the refreshing operation of the FCRAM. As shown in FIG. 7, in reading-out/writing-in of data, only one selected sub-block 3 and the sense amplifiers 4 on both sides thereof are activated. Meanwhile, as shown in FIG. 8, in refreshing, sub-blocks 3 (four sub-blocks 3 which are in a row selected by the row decoder 1) and the sense amplifiers 4 on these both sides are activated in order to reduce the number of the refreshing.
However, in the conventional overdrive type sense amplifier, all the four power supply circuits PS1 to PS4 which drive the sense amplifiers 4 operate concurrently to supply voltage and its operations are the same in the reading-out/writing-in of data and in the refreshing. Therefore, a load which is imposed by each power supply circuit PS1 to PS4 on the sense amplifier 4 in the activated area is different between the reading-out/writing-in of data and the refreshing.
Namely, in the reading-out/writing-in of data as shown in FIG. 7, the loads from the four power supply circuits PS1 to PS4 are imposed concentratedly on one activated area, whereas in the refreshing as shown in FIG. 8, the loads from the four power supply circuits PS1 to PS4 are imposed dispersively on the four activated areas.
Here, if the overdrive time tovd is designed according to, for example, the refreshing time, the driving capacity to the sense amplifiers becomes excessive in the reading-out/writing-in of data, which results in the situation as shown in FIG. 5D. In this situation, too much voltage is applied to the bit line pair BL and /BL to decrease its reliability thereby. Further, shorts of the bit line pair BL and /BL are caused and the precharge level rises than usual in precharging, which causes a problem that the reading-out of data from another memory cell is affected in the following operation of the reading-out of data.
Meanwhile, if the overdrive time tovd is designed according to the reading-out/writing-in of data, the driving capacity to the sense amplifiers becomes insufficient in the refreshing, which results in the situation as shown in FIG. 5E. In this situation, the amplification of the bit line voltage is delayed, which causes a problem that the normal reading-out of data cannot be operated.
To solve the aforesaid problems, it is possible to think about controlling the overdrive time tovd to be different between the reading-out/writing-in of data and the refreshing so that the appropriate load is imposed in each case of the reading-out/writing-in of data and the refreshing. However, this kind of processing is complex and it is necessary to provide the control circuit like this separately, which causes to complicate the circuit structure.
It is an object of the present invention to realize appropriate overdrive of a sense amplifier of an activated area in each case of a reading-out/writing-in of data and a refreshing, without complicating a circuit structure.
In a semiconductor memory device according to the present invention, the sense amplifiers which are provided in a same bank are divided into groups, the sense amplifiers in each group are connected to a common power supply line which is independent by the group, and the power supply line of each group is connected to a power supply circuit which is independent.
Thereby, the ratio of the activated sense amplifiers to the driven power supply circuits can be equalized between a first operation mode in which at least one sense amplifier is activated in the bank and a second operation mode in which the increased number of sense amplifiers are activated in the bank than in the first operation mode, which makes it possible to equalize the loads of the sense amplifiers between the first operation mode and the second operation mode, when seen from the respective power supply circuits.